Bit Error Rate Testers
IMEX support two BERT solutions from Tektronix and Picosecond Pulse Labs (PSPL).
Bit Error Rate Testers that deliver unprecedented flexibility and performance to help compress your product development cycles and reduce verification testing costs. Quickly and confidently identify errors in digital bit streams with these highly advanced test and measurement instruments. Learn more about Tektronix Bit Error Rate Testers:
- The BERTScope® BSA Series Bit Error Rate Testers provide a new approach to signal integrity measurements of serial data systems by combining the confidence of a BERT and the insight of an Oscilloscope.
- The BERTScope® CR Series Clock Recovery Instruments deliver the flexibility and accuracy you need for compliance measurements in conjunction with Bit Error Rate Testers and Sampling Oscilloscopes.
- The BERTScope® DPP Series Digital Pre-emphasis Processor takes in single-ended inputs of data and clock and condition the signal by adding controllable amounts of pre-emphasis for use with Bit Error Rate Testers.
- The BitAlyzer® BA Series Bit Error Rate Testers address signal integrity and BER issues faced by designers of sophisticated electronic and satellite communication system designs.
Features & Benefits
- Pattern Generation and Error Analysis, High-speed BER Measurements up to 26 Gb/s
- Integrated, Calibrated Stress Generation to Address the Stressed Receiver Sensitivity and Clock Recovery Jitter Tolerance Test Requirements for a Wide Range of Standards
- Sinusoidal Jitter to 100 MHz
- Random Jitter
- Bounded, Uncorrelated Jitter
- Sinusoidal Interference
- Spread Spectrum Clocking
- PCIe 2.0 Receiver Testing
- F/2 Jitter Generation for 8xFC and 10GBASE-KR Testing
- Electrical Stressed Eye Testing for:
- PCI Express
- 10/40/100 Gb Ethernet
- Fibre Channel
- USB 3.0
- Jitter Tolerance Compliance Template Testing with Margin Testing
- Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates
- Integrated Eye Diagram Analysis with BER Correlation
- Optional Jitter Map Comprehensive Jitter Decomposition – with Long Pattern (i.e. PRBS-31) Jitter Triangulation to Extend BER-based Jitter Decomposition Beyond the Limitations of Dual Dirac TJ, DJ, and RJ for a Comprehensive Breakdown of Jitter Subcomponents
- Patented Error Location Analysis™ enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis
- Design Verification including Signal Integrity, Jitter, and Timing Analysis
- Design Characterization for High-speed, Sophisticated Designs
- Certification Testing of Serial Data Streams for Industry Standards
- Design/Verification of High-speed I/O Components and Systems
- Signal Integrity Analysis – Mask Testing, Jitter Peak, BER Contour, Jitter Map, and Q-factor Analysis
- Design/Verification of Optical Transceivers
For a full datasheet on our Tektronix BERT offering please click here.
PSPL’s line of PatternPro serial data test instruments enables testing of the latest high-speed serial data standards by addressing critical configuration and cost issues. The PatternPro line includes SDG Pattern Generators and SDA Error Detectors that provide high-performance, flexible Bit Error Test solutions. With PatternPro test suites, users are finally able to comprehensively test critical multi-channel product performance parameters such as cross-talk immunity and multi-channel functionality.
Example of a 32Gb/s 4 Channel BERT System with modular pattern generator and error checker setup.